pipeline/ bus size control effective address bus effective address bus dedicated alu bus barrel shifter, adder multiply/ divide register file decode and sequencing control rom instruction decoder 3-decoded instruction queue prefetcher/ limit checker limit and attribute pla descriptor registers 3-input adder page cache adder request prioritizer address driver protection test unit alu control alu control instruction instruction code stream 32 32 32 34 32 segmentation unit paging unit bus control hold, intr, nmi, error , busy , reset, hlda, flt be3 -be0 a31-a2 m/io , d/c , w/r , lock , ads , bs16 , na , ready d31-d0 AM386DX/dxl block diagram 32 bit control attribute pla and prefetch predecode mux/ trans- ceivers status flags 16-byte code queue displaement bus physical address bus control code fetch/page table fetch linear address bus internal control bus 32
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